Directory-Based Cache Coherence: A Key to Efficient CPU Communication

When it comes to managing data coherence across multiple cores, directory-based cache coherence plays a crucial role. This approach is employed in Intel Core i7 processors, specifically in the Sandybridge-family CPUs with a ring bus architecture.

In this design, each core has its own L1d and L2 caches, which are connected through a shared inclusive Last-Level Cache (LLC) or Meta (元) cache. The LLC acts as a directory, keeping track of the state of each cache line (MESI state) and which core owns it exclusively. This information is used to filter out unnecessary snooping requests and minimize the impact on performance.

When a core requires data from another core's cache, it sends a request over the ring bus, which is routed to the relevant slice of the LLC. The LLC checks its tags and determines whether the requested line is in Modified state on another core. If so, it generates a message asking that core to write back the data.

In Intel CPUs, the shared inclusive LLC also records which core has a private copy of a line, allowing for efficient cache coherence management. This approach avoids broadcasting snooping requests, which would lead to increased latency and decreased performance.

For instance, when Core #0 on an Intel CPU requires data from a line that is present in Modified state on Core #1's L2 or L1d cache, the LLC will generate a message asking Core #1 to write back the data. The message arrives at the ring bus stop for Core #1 and gets written back by its LLC.

In this way, directory-based cache coherence enables efficient communication between cores, minimizing the need for snooping requests and ensuring that cache lines are consistently updated across all cores. This approach has been widely adopted in modern CPUs, including Intel's Sandybridge-family processors and AMD's MOESI-based designs. By leveraging a shared inclusive LLC as a snoop filter and MESI state tracker, these architectures achieve efficient and scalable cache coherence management.

Directory based cache coherence